This Wall Street Journal ($) article reports on the development of an experimental computer chip at the University of Texas that is like a chameleon in that its able to change its function according to the task at hand.
Steve Keckler, a UT computer scientist and a leader of the design effort, believes that the chip can be configured to perform as a specialized chip for devices such as cell phones and digital music players or even serve as a powerful central processor in a desktop or other general-purpose computer. The team hopes to have a prototype of the device finished in about a year and ready for commercialization by the end of this decade. The Defense Advanced Research Projects Agency, a Defense Department agency, is funding the UT team’s development.
If the chip works as planned, it will run at a top speed of 10 gigahertz and perform one trillion operations (meaning individual computing tasks) per second. In comparison, Intel Corp.’s current top-speed Pentium 4 processor runs at 3.4 gigahertz and delivers 6.8 billion operations per second. The anticipated performance has led the design team to dub the device a “supercomputer on a chip.”
The UT team has nicknamed their design “Trips,” for Tera-Op Reliable Intelligently Adaptive Processing System. The term tera-op refers to the targeted one trillion operations per second. The system would divide individual processing cores on the chip into tiny sections that could change automatically for several predetermined functions. The idea is that the processing cores would morph as instructions flowed in. Each chip could contain many processing core, which would enable a single chip to perform multiple functions simultaneously while optimizing for each. Conventional chips generally do only one thing at a time. Moreover, the distributed architecture of the UT team’s design would reduce clock delays, which limit the performance of conventional chips.